Everything related to digital electronics is related to time. Timer, counter, frequency, pulse width, clock and time are the most common words one may find in this arena. Microcontrollers just like humans need heart-beats and these come from clock sources. Apart from system clock, timers are clock sources that can be used as heart-beats for various applications. All modern micros are embedded with timer-counter modules and generally they are used for generating time bases, counting pulses, measuring time periods of waveforms, generating pulse width modulation (PWM) signals, triggering external devices and timing special events. STM32 micros have several timers designed for such applications. However unlike most 8-bit micros which possess two/three timers with limited functionalities, the timers of STM32s are very elaborate and complex. This explains why documentations related to timer modules take about 25% of any STM32 reference manual.
Before we begin exploring STM32 timers, I must point out that I won’t be able to cover every aspect of all timer modules as they are vast and need lot of explanations, something which is beyond the scope of a single post. This is why in this issue we shall explore the very basics of timer modules enough to get STM32 timers to work.
In any microcontroller there is at least one general purpose input-output port. STM32 is a not different breed and as expected it also has several GPIO ports. These ports are usually named GPIOA, GPIOB, etc. but unlike most 8/16-bit micros these ports are 16 bit wide. Thus, in general, every port has 16 IO pins. Port pins have several modes of operation and this is what that makes them both robust and complex at first. In development boards the IO port pin naming is cut short and so we’ll find PA0, PB12, etc. instead of GPIOA0, GPIOB12, etc. Even in the reference manuals this short naming is used widely. In the end every I/O pin is general purpose in nature.
Key points with STM32’s GPIO
- Upon any reset event all GPIOs are floating inputs. This prevents any accidental damage to GPIOs in the event of emergency.
- All GPIO registers are needed to be accessed with 32 bit words. This is mandatory.
- Reserved bits for any GPIO register are kept at reset values i.e. 0.
- For every GPIO port there are seven registers but the only the first four are the most important ones. The rest can be ignored most of the times.
- These important GPIO registers per port are CRL, CRH, IDR and ODR. The rest three registers for GPIO ports can be avoided at the beginning.
- For bit set and for bit clear, operations REGx |= (1 << bit) and REGx &= ~ (1 << bit) respectively are very handy and efficient. However MikroC compiler provides bit level access though its internal header file coding like this GPIOB_BSRRbits.BS15. We can use this method or the other one.
- Some IOs are 5V tolerant and are label “FT” in datasheets and other docs. The rest of the I/O pins are not that tolerant and so 3.3V operation should always be ensured. STM32 has a maximum VDD tolerance of 4V but this value shouldn’t be used in any situation for safe operation. Best is to avoid 5V use with GPIOs whenever possible. This will help in avoiding accidental damage to the micro due to common mistakes.
- Unused GPIO pins should be kept at reset state or tied to ground with 10kΩ resistors so that they remain either as floating inputs or safely connected to ground though it’s not a must.
- I/O pins can source or sink currents up to 25mA. Thus direct LED drive is possible with them. To drive loads that need more than this value, we must use external BJTs, MOSFETs, optocouplers, transistor arrays or other driver devices.
- I/O pins should not directly drive inductive or capacitive loads.
- Care should be taken to avoid driving outputs beyond 50MHz. This is the maximum I/O pin frequency rating.
- CRL/H registers essential set GPIO pin operating mode independently as according to the table below:
- CRL sets GPIOs from 0 – 7 while CRH sets from 8 – 15. All IO ports are 16 bit wide unlike common 8 bit micros like PIC or AVR.
I remember that once in the beginning I said that I don’t want to buy a programmer/debugger hardware for learning a new MCU like the STM32 and also STM32s already come with built-in bootloader to facilitate programming via USART just like Arduino. Still the second is true. Well what about the first? To my own surprise I actually acquired a number of STM32-related stuffs since the time I started playing and exploring them. I actually bought both ST-Link 1 and 2 programmer-debuggers and several STM32 boards from Waveshare Electronics (http://www.wvshare.com). I believe learning new stuffs is more valuable than anything else.
ST-Link 1 (AKA ST-Link) and ST-Link v2 are both basically the same programmer/debugger hardware with some minor exceptions. ST-Link 2 has 5V tolerance for JTAG interface, it has a bicolour status LED and it also has a separate programming interface for STM8 micros unlike ST-Link 1. There is also an ISOL version of ST-Link2 that galvanically isolates it from its target using optoelectronics.
STM32 micros as we know are high-end micros and this high-end tag is not only due to its memory, speed and hardware richness. An advanced micro like this also needs advanced internal supporting hardware. Most of us know about watchdog timers from previous experiences with common 8 bit MCUs like AVR and PIC. However when it comes to STM32 the idea of watchdog circuitry is elaborated. The options available for clock are also enhanced in the STM32 micros. In this post, we will see some of these supporting internal hardware. We will examine the use and operation of two different watchdog timers – Independent Watchdog (IWDG) and Window Watchdog (WWDG), and the clock options usually found in common STM32 micros.
In a robust microcontroller like the STM32 there are several options for clock. At first the whole stuff may look a bit complex. Indeed it is complicated but not too difficult to understand. The simplified block diagram below shows the common clock arrangement inside a STM32F103 series MCU.
STM32F103 Internal Clock Arrangement (Source: The Insiders Guide to the STM32 ARM based Microcontroller from HITEX, http://www.hitex.com/fileadmin/pdf/insiders-guides/stm32/isg-stm32-v18d-scr.pdf)
In my earlier post on STM32 GPIOs I showed how to flash a LED with variable delay times. That example was based on polling method where the code continuously monitored the logic state of a GPIO input pin attached to a push button to determine the delay amount. Obviously that won’t be an efficient technique when a program will be of a considerable size and complexity. This is simply so because the CPU will have to check the GPIO’s logic state every time the super-loop (while (1) loop in the main function) repeats and the push button will also not be responsive during the software delay function calls. Thus the overall performance is poor and not real-time. To get rid of these issues, we’ll need to use external interrupts – a vital feature in every common microcontroller.
STM32F1xx series are ARM Cortex M3 based MCUs. The Cortex M3 based MCUs have a sophisticated and yet easy to use interrupt system called the Nested Vectored Interrupt Controller (NVIC). It ensures low latency and high performance. There are several features of the NVIC and these are handled by the compiler. Our job is simply to enjoy the lightning fast interrupt responses owing to the NVIC. In many MCUs’ interrupt system, interrupt priority can be set and Reset has the highest interrupt priority over anything else. The same things go for STM32s too. However at present I’m not going to go that deep as that’s not needed for now. In some upcoming post may be I’ll discuss the NVIC in details. As per STM32’s reference manuals for more information on exceptions and NVIC programming read Chapter 5 Exceptions and Chapter 8 Nested Vectored Interrupt Controller of the ARM Cortex-M3 Technical Reference Manual. There are other interrupts that are related to RTC, timer, etc. We won’t also look into them in this post. We will learn about them when we learn about the related hardware with them.