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Feature of STM32 RTC Block<\/h4>\n
The embedded RTC of a STM32 micro is an independent binary-coded-decimal (BCD) timer counter. The RTC core consists of counters, prescalers, clock dividers, alarm data registers, etc. Like with any standard RTC chip, the embedded RTC can be used to provide a full-featured software-based calendar along with alarm functions. However more needs to be done on the software end rather than the hardware end. When using RTC chips, it is only required to read or write individual date-time registers. In a STM32 micro, we need to do more than that as no separate date-time registers exist.<\/p>\n
Resetting or waking up the MCU from a sleep\/standby mode does not reinitializes time once set. It gets even better if there is a battery backup on battery backup (VBAT<\/em><\/strong>) pin. All VDDs of a STM32 can be turned off or in other words the entire MCU core can be fully shut down but the battery backup keeps the RTC and the backup domain running. Thus time is not varied or lost during powered down and sleep modes. Key features of the STM32 embedded RTC are highlighted below:<\/p>\n Shown below is the block diagram of the embedded RTC for a typical STM32F10x microcontroller.<\/p>\n The RTC comprises of two major components. The first is the APB1 bus interface. The APB1 bus interface consists of clock dividers and is used to connect with APB1 bus. This interface also consists of a set of 16-bit registers that can be read\/written by APB1 bus operations.<\/p>\n The other component is the RTC core. It consists of a group of programmable counters divided into two modules. The first module is the RTC prescaler module. This module generates a programmable time base of one second (TR_CLK<\/em><\/strong>) by using a 20-bit programmable divider. The other module is a 32-bit wide programmable counter that is used to keep counts of seconds. Since it is 32-bit wide, with a TR_CLK<\/em><\/strong> period of one second, it can record up to 4,294,967,296 seconds or roughly a century \u2013 a pretty big time for any machine or a human lifetime.<\/p>\n There are registers for alarms which work in a similar manner as compare match interrupt in a timer. Whatever stored in the alarm registers is compared with the values in the counter registers. An alarm event occurs when both register sets have the same value.<\/p>\n The RTC core is totally independent of the RTC APB1 interface just like the Independent Watchdog Timer (IWDG). RTC registers, counters, alarms and flags are accessible via APB1 interface but the counter registers are updated by a separate RTC clock. As illustrated in the block diagram, the RTC core keeps functioning even if the APB1 bus is unpowered. This is only possible with power supply backup using a battery or a supercapacitor.<\/p>\n The good part of RTC registers is the fact that most of them are 16-bit wide while the rest are even less than a byte wide. There are two RTC control registers which set RTC properties. The rest of the stuffs are counters and clock dividers. Check the RTC register map below:<\/p>\n The RTC_CRH<\/em><\/strong> register is the first control register which is responsible for setting up interrupts related to the RTC module. There are three types of interrupts and these are alarm, overflow and second interrupt.<\/p>\n The other control register is the RTC_CRL<\/em><\/strong>. This register consists of several flags that trigger on events like counter overflow, alarm, RTC status, etc.<\/p>\n Then we see the RTC prescaler load registers as RTC_PRLL<\/em><\/strong> and RTC_PRLH<\/em><\/strong>. Together they are 20-bit wide. These two registers are used to divide the RTC clock source frequency. These registers are write protected and special steps are needed to disable this protection. In my example I used an external 32.768 kHz crystal oscillator and so I loaded 32,767 in these registers to get one second. Thus the formula for getting TR clock (TR_CLK<\/em><\/strong>) frequency can be realized as:<\/p>\n The RTC counter registers \u2013 RTC_CNTL <\/em><\/strong>and RTC_CNTH<\/em><\/strong> are the most important registers as they keep the count of the seconds or in other words time. These registers are each 16-bit wide. Once set these registers return current time. Writing these registers is only possible by entering configuration mode.<\/p>\n Finally there are two 16-bit registers dedicated for alarm. RTC_ALRL<\/em><\/strong> and RTC_ALRH<\/em><\/strong> hold alarm time data. This set of registers is just like a typical data registers or RAM location. When an alarm is set the alarm register values are compared with RTC counter register values. An alarm is triggered when the values in these registers match. Again modification to these registers is only possible in configuration mode. Apart from these backup domain registers we will be needing some other registers for additional functionalities of the backup and the RTC block. Those registers won\u2019t be needing for now and won\u2019t be discussed here. We\u2019ll be needing the Power Control (PWR) <\/em><\/strong>registers for disabling backup domain write protect scheme. Power control registers will be dealt separately in details in another post.<\/p>\n Just as we configure the main HSE\/HSI\/ PLL clock, we will be configuring the LSE\/LSI clock. We will be needing to configure some registers of the Reset and Clock Control (RCC)<\/em><\/strong> block for this purpose. RCC_BDCR<\/em><\/strong> and RCC_CSR<\/em><\/strong> registers will be needed to select RTC clock source and enable low speed (LSI and LSE) clock sources.<\/p>\n In my version of SPL, I took care of all of these stuffs. We just have to apply them.<\/p>\n The hardware setup for this example is very simple. For this demo I used a STM32F103C8T6 micro, a 2×16 alphanumerical LCD connected to GPIOB port pins and four push buttons connected to GPIOA port pins. The buttons are used for setting time. Since I used LSE clock, a 32.768 kHz clock crystal is connected to PC14 and PC15 pins. I also used an 8MHz external crystal for RCC. Using PLL, the clock speed is multiplied to generate 72 MHz system clock. A 3.6V, 250mAH backup lithium ion battery is connected to the VBAT pin. This keeps the backup domain and the RTC core powered.<\/p>\n The RCC\u2019s internal setup is as follows:<\/p>\n\n
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Functional Description<\/h4>\n
<\/a><\/p>\nRTC Registers<\/h4>\n
<\/a><\/p>\n<\/a>Next are the RTC divider registers \u2013 RTC_DIVL<\/em><\/strong> and RTC_DIVH<\/em><\/strong>. The purpose of these registers is to obtain a higher resolution clock than the second count, e.g. 100ms. These are not usually used.<\/p>\n
\nApart from the registers within the RTC block, we also need to deal with the registers of the backup block. The backup domain of a STM32 MCU is somewhat like an EEPROM memory but it is not essentially a true EEPROM memory as it needs battery backup on VBAT<\/em><\/strong> pin to hold data. The backup domain consists a total of 42 data registers, each 16-bit wide. These are usually used to retain user data when a STM32 micro\u2019s main core is powered down or in standby mode. Thus backup data registers can be realized as battery-backed RAM storages.<\/p>\n
\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\nProcedure to Configure the RTC Block<\/h4>\n
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Hardware setup<\/h4>\n
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