{"id":14138,"date":"2018-03-30T15:33:01","date_gmt":"2018-03-30T19:33:01","guid":{"rendered":"http:\/\/embedded-lab.com\/blog\/?p=14138"},"modified":"2023-09-06T02:59:37","modified_gmt":"2023-09-06T06:59:37","slug":"more-on-ti-msp430s","status":"publish","type":"post","link":"https:\/\/embedded-lab.com\/blog\/more-on-ti-msp430s\/","title":{"rendered":"More on TI MSP430s"},"content":{"rendered":"
<\/h5>\n
This post is a sequel of the first post on TI MSP430 micros here<\/a>.<\/h5>\n

\"5529\"<\/a><\/h1>\n

<\/p>\n

Low Power Modes (LPM)<\/h1>\n

From the smartwatches in our wrists to the vehicles we use for transportation, many modern electronic gadgets and gizmos are battery-powered. Some are even dependent on renewable energy sources like solar energy. In such devices, there is always an inherent energy crisis and so saving energy is a must in such designs for prolonged usage. At present there is hardly any microcontroller in the market that does not come equipped with energy-saving schemes or low power modes of operation. MSP430s were mainly designed for battery-backed instruments and it is no surprise that they come loaded with the some of the best possible energy-saving mechanisms.<\/p>\n

There six modes of operation of which five are low power modes. These are as follows:<\/p>\n

\"Modes\"<\/a><\/p>\n

Of these six modes, three modes are mostly used \u2013 Active Mode (AM), LPM0 and LPM3. In Active Mode, the typical self-consumption of a MSP430 device is roughly about 300\u00b5A with nothing connected to it. In LPM0 the self-consumption is about a third of active mode while in LPM3, this consumption is just about 1\u00b5A. These figures tell us how much energy efficient MSP430s are.<\/p>\n

Entering and exiting LPM is easy in terms of coding. However, the most common question that coders face with LPMs is how to get back to active mode or some other low power mode from a given low power mode. Well, it is pretty simple and it is accomplished with interrupts. It is up to coders to decide how to manage interrupts, clock sources and what do to after waking up from a LPM condition. Note that in LPMs, the CPU is disabled and so any task that requires CPU\u2019s intervention is stalled. Since the CPU and some clocks are halted in LPMs, don\u2019t even think that the tasks depending on them will be magically done. For instance, if a code has entered LPM3 and a timer is being driven with SMCLK, we should not expect it to tick because in LPM3, SMCLK is turned off. Organizing the code in a decent and well-planned manner is the secret behind successfully implementing LPMs.<\/p>\n

Code Example<\/h2>\n
#include<\/strong> <msp430.h><\/em><\/span><\/pre>\n
#include<\/strong> \"delay.h\"<\/em><\/span><\/pre>\n
<\/pre>\n
<\/pre>\n
void<\/strong> GPIO_graceInit<\/strong>(void<\/strong>);<\/em><\/span><\/pre>\n
void<\/strong> BCSplus_graceInit<\/strong>(void<\/strong>);<\/em><\/span><\/pre>\n
void<\/strong> System_graceInit<\/strong>(void<\/strong>);<\/em><\/span><\/pre>\n
void<\/strong> WDTplus_graceInit<\/strong>(void<\/strong>);<\/em><\/span><\/pre>\n
<\/pre>\n
<\/pre>\n
#pragma<\/strong> vector = PORT1_VECTOR<\/em><\/span><\/pre>\n
__interrupt<\/strong> void<\/strong> PORT1_ISR_HOOK<\/strong>(void<\/strong>)<\/em><\/span><\/pre>\n
{<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 LPM2_EXIT;<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1OUT |= BIT6;<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1IFG = 0x00;<\/em><\/span><\/pre>\n
}<\/em><\/span><\/pre>\n
<\/pre>\n
<\/pre>\n
void<\/strong> main<\/strong>(void<\/strong>)<\/em><\/span><\/pre>\n
{<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 unsigned<\/strong> char<\/strong> s = 0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Stop watchdog timer from timing out during initial start-up. *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 WDTCTL = WDTPW | WDTHOLD;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* initialize Config for the MSP430 GPIO *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 GPIO_graceInit<\/strong>();<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* initialize Config for the MSP430 2xx family clock systems (BCS) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 BCSplus_graceInit<\/strong>();<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* initialize Config for the MSP430 System Registers *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 System_graceInit<\/strong>();<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* initialize Config for the MSP430 WDT+ *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 WDTplus_graceInit<\/strong>();<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 while<\/strong>(1)<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 {<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 for<\/strong>(s = 0; s < 9; s++)<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 {<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 P1OUT ^= BIT0;<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 delay_ms<\/strong>(160);<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 }<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 P1OUT &= ~BIT6;<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 LPM2;<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 };<\/em><\/span><\/pre>\n
}<\/em><\/span><\/pre>\n
<\/pre>\n
<\/pre>\n
void<\/strong> GPIO_graceInit<\/strong>(void<\/strong>)<\/em><\/span><\/pre>\n
{<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: GPIO_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User initialization code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: GPIO_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 1 Output Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1OUT = BIT3;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 1 Direction Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1DIR = BIT0 | BIT6;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 1 Resistor Enable Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1REN = BIT3;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 1 Interrupt Edge Select Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1IES = BIT3;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 1 Interrupt Flag Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1IFG = 0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 1 Interrupt Enable Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P1IE = BIT3;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 2 Output Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P2OUT = 0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 2 Port Select Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P2SEL &= ~(BIT6 | BIT7);<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 2 Direction Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P2DIR = 0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 2 Interrupt Edge Select Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P2IES = 0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Port 2 Interrupt Flag Register *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 P2IFG = 0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: GPIO_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: GPIO_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
}<\/em><\/span><\/pre>\n
<\/pre>\n
<\/pre>\n
void<\/strong> BCSplus_graceInit<\/strong>(void<\/strong>)<\/em><\/span><\/pre>\n
{<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: BCSplus_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User initialization code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: BCSplus_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/*<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * Basic Clock System Control 2<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * SELM_0 -- DCOCLK<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * DIVM_0 -- Divide by 1<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~SELS -- DCOCLK<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * DIVS_0 -- Divide by 1<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~DCOR -- DCO uses internal resistor<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * Note: ~<BIT> indicates that <BIT> has value zero<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 BCSCTL2 = SELM_0 | DIVM_0 | DIVS_0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 if<\/strong> (CALBC1_1MHZ != 0xFF)<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 {<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* Follow recommended flow. First, clear all DCOx and MODx bits. Then<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * apply new RSELx values. Finally, apply new DCOx and MODx bit values.<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 DCOCTL = 0x00;<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 BCSCTL1 = CALBC1_1MHZ;\u00a0\u00a0\u00a0\u00a0\u00a0 \/* Set DCO to 1MHz *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 DCOCTL = CALDCO_1MHZ;<\/em><\/span><\/pre>\n
\u00a0 \u00a0\u00a0}<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/*<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * Basic Clock System Control 1<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * XT2OFF -- Disable XT2CLK<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~XTS -- Low Frequency<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * DIVA_0 -- Divide by 1<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * Note: ~XTS indicates that XTS has value zero<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 BCSCTL1 |= XT2OFF | DIVA_0;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/*<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \u00a0* Basic Clock System Control 3<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * XT2S_0 -- 0.4 - 1 MHz<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * LFXT1S_2 -- If XTS = 0, XT1 = VLOCLK ; If XTS = 1, XT1 = 3 - 16-MHz crystal or resonator<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * XCAP_1 -- ~6 pF<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 BCSCTL3 = XT2S_0 | LFXT1S_2 | XCAP_1;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: BCSplus_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: BCSplus_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
}<\/em><\/span><\/pre>\n
<\/pre>\n
<\/pre>\n
void<\/strong> System_graceInit<\/strong>(void<\/strong>)<\/em><\/span><\/pre>\n
{<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: System_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User initialization code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: System_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* Clear oscillator fault flag with software delay *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 do<\/strong><\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 {<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/\/ Clear OSC fault flag<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 IFG1 &= ~OFIFG;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/\/ 50us delay<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 __delay_cycles<\/strong>(50);<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 } while<\/strong> (IFG1 & OFIFG);<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/*<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * SR, Status Register<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~SCG1 -- Disable System clock generator 1<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~SCG0 -- Disable System clock generator 0<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~OSCOFF -- Oscillator On<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~CPUOFF -- CPU On<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * GIE -- General interrupt enable<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \u00a0*<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * Note: ~<BIT> indicates that <BIT> has value zero<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 __bis_SR_register<\/strong>(GIE);<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: System_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: System_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
}<\/em><\/span><\/pre>\n
<\/pre>\n
<\/pre>\n
void<\/strong> WDTplus_graceInit<\/strong>(void<\/strong>)<\/em><\/span><\/pre>\n
{<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: RTC_B_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User initialization code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: RTC_B_graceInit_prologue) *\/<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/*<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * WDTCTL, Watchdog Timer+ Register<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * WDTPW -- Watchdog password<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * WDTHOLD -- Watchdog timer+ is stopped<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~WDTNMIES -- NMI on rising edge<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~WDTNMI -- Reset function<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~WDTTMSEL -- Watchdog mode<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~WDTCNTCL -- No action<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~WDTSSEL -- SMCLK<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~WDTIS0 -- Watchdog clock source bit0 disabled<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * ~WDTIS1 -- Watchdog clock source bit1 disabled<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 * Note: ~<BIT> indicates that <BIT> has value zero<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0\u00a0 *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 WDTCTL = WDTPW | WDTHOLD;<\/em><\/span><\/pre>\n
<\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE START (section: RTC_B_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* User code *\/<\/em><\/span><\/pre>\n
\u00a0\u00a0\u00a0 \/* USER CODE END (section: RTC_B_graceInit_epilogue) *\/<\/em><\/span><\/pre>\n
}\n<\/em><\/span><\/pre>\n
Simulation<\/h2>\n
\"SIM\"<\/a><\/p>\n
The simulation log of Proteus shown below shows when the internal oscillators started and stopped. These indicate LPM and AM states.<\/p>\n
\"SIM<\/a><\/p>\n
Explanation<\/h2>\n
This is a pretty straight example. The code here works by first flashing the Launchpad board\u2019s red LED for some time. During this time the MSP430 is running in active mode. After the flashing is over, the MP430 micro enters LPM2 state. Note that in LPM2 state all except the DC generator and ACLK are turned off. At this stage to wake up and exit LPM2, an interrupt is needed. Here this interrupt is generated by the external interrupt caused by pressing the Launchpad board\u2019s user button. In the interrupt service routine (ISR), LPM2 is left and is indicated by a brief flash from the Launchpad board\u2019s green LED. After executing the ISR, the code returns to main function and the process repeats again.<\/p>\n
Note that for LPMs, there is no segment in Grace and LPM code definitions can be found in device\u2019s header files.<\/p>\n
Demo<\/h2>\n
\"LPM<\/a> \"LPM<\/a><\/p>\n