{"id":4874,"date":"2012-04-26T19:22:27","date_gmt":"2012-04-26T23:22:27","guid":{"rendered":"http:\/\/embedded-lab.com\/blog\/?p=4874"},"modified":"2012-07-30T09:29:12","modified_gmt":"2012-07-30T13:29:12","slug":"interfacing-an-external-adc-chip-to-fpgacpld","status":"publish","type":"post","link":"https:\/\/embedded-lab.com\/blog\/interfacing-an-external-adc-chip-to-fpgacpld\/","title":{"rendered":"Interfacing an external ADC chip to FPGA\/CPLD"},"content":{"rendered":"<p>Chris (from <a href=\"http:\/\/www.pyroelectro.com\" target=\"_blank\">PyroElectro<\/a>) has posted an article on <a href=\"http:\/\/www.pyroelectro.com\/tutorials\/cpld_board\/index.html\" target=\"_blank\">interfacing an external ADC chip to FPGAs and CPLDs<\/a>, which do not have A\/D capabilities built-in. He illustrates the idea with an Altera EPM7128 and a MAX150 8-bit analog to digital converter IC. The test analog signal is derived using a potentiometer and the converted digital output is shown using an LED bargraph display. The interface between the CPLD and ADC has been implemented in VHDL.<\/p>\n<div id=\"attachment_4877\" style=\"width: 580px\" class=\"wp-caption aligncenter\"><a href=\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2012\/04\/cpld_top.jpg\"><img loading=\"lazy\" decoding=\"async\" aria-describedby=\"caption-attachment-4877\" class=\"size-full wp-image-4877\" title=\"cpld_top\" src=\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2012\/04\/cpld_top.jpg\" alt=\"\" width=\"570\" height=\"413\" srcset=\"https:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2012\/04\/cpld_top.jpg 570w, https:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2012\/04\/cpld_top-550x398.jpg 550w\" sizes=\"auto, (max-width: 570px) 100vw, 570px\" \/><\/a><p id=\"caption-attachment-4877\" class=\"wp-caption-text\">Interfacing an ADC to CPLD<\/p><\/div>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Chris (from PyroElectro) has posted an article on interfacing an external ADC chip to FPGAs and CPLDs, which do not have A\/D capabilities built-in. He illustrates the idea with an Altera EPM7128 and a MAX150 8-bit analog to digital converter IC. The test analog signal is derived using a potentiometer and the converted digital output is shown using an LED bargraph display. The interface between the CPLD and ADC has been implemented in VHDL. &nbsp;<\/p>\n","protected":false},"author":1,"featured_media":4877,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[227,183],"tags":[44,430,1315],"class_list":["post-4874","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","category-tips-and-tricks","tag-adc","tag-cpld","tag-fpga"],"_links":{"self":[{"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/posts\/4874","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/comments?post=4874"}],"version-history":[{"count":5,"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/posts\/4874\/revisions"}],"predecessor-version":[{"id":5680,"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/posts\/4874\/revisions\/5680"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/media\/4877"}],"wp:attachment":[{"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/media?parent=4874"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/categories?post=4874"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/embedded-lab.com\/blog\/wp-json\/wp\/v2\/tags?post=4874"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}