![\"Clock](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/Clock-Internal-1024x366.png\")
<\/a>STM32F103 Internal Clock Arrangement (Source: The Insiders Guide to the STM32 ARM based Microcontroller<\/strong> from HITEX, http:\/\/www.hitex.com\/fileadmin\/pdf\/insiders-guides\/stm32\/isg-stm32-v18d-scr.pdf)<\/p><\/div>\n <\/p>\n This view give a straight forward insight of the clock hardware. When it comes to software, it is very easy to configure this vast array of hardware. The good stuff about MikroC PRO for ARM and the good news for us is the fact that its IDE already ported an easy-to-use clock configuration tool just as MikroElektronika added fuse configuration tools for its PIC and AVR compilers.<\/p>\n This clock configuration option pops up whenever we start a new project. Alternatively we can go to the Project<\/i><\/b> tab in the MikroC IDE and select Edit Project<\/i><\/b>. If configured properly then it is not needed to manually code clock settings by accessing Reset Clock Control<\/i><\/b> (RCC<\/i><\/b>) registers. In fact we won\u2019t be needing to add the generated values of the RCC registers anywhere in the code. These values are automatically integrated with the user code. However this feature doesn\u2019t limit us to code RCC registers on our own.<\/p>\n Now let\u2019s check out what clock sources are there in a STM32 micro. There are two basic types of clock and they are themselves divided into two speed categories. These are as follows:<\/p>\n There are prescalars at various points and these can be used to configure individual clocks of various parts of the STM32 MCU. This feature not only ensures energy saving but also aid in running various components of the micro at optimum speeds. An optional clock security unit is also available for use that can switch to HSI should HSE fail for some reason. Apart from different clock sources there is a Phase-Lock-Loop (PLL) module that can multiply either HSE or HSI to generate yet larger values of clock. In fact an 8MHz HSI or HSE clock is passed through the PLL with 9 as multiplying factor to generate full speed 72MHz clock. This also why most ready-made STM32 development boards like the ones I use for demos come with an 8MHz crystal oscillator.<\/p>\n Waveshare’s STM32 development board<\/p><\/div>\n Though out this post I have used a Waveshare\u2019s Open103R STM32F103RC delevopment board – http:\/\/www.wvshare.com\/product\/Open103R-Standard.htm<\/a>. Like I said about development board and crystal oscillators in them this board also comes with an 8MHz and a 32.768 kHz clock crystal. As much as I have used Waveshare STM32 goods I have come across basically three categories of STM32 ARM development boards. Firstly they have Open<\/i> series development boards that pack all of the features one might expect in a microcontroller development board and these boards come with easy to interface headers for connecting to external hardware like CAN communication modules, RTC modules, LCDs, etc. Secondly they also have a plug-in-module (PIM) based Open series boards that have minimum hardware and they can used either separately or with an extension motherboard. Thirdly they have Port <\/i>series boards that are lighter versions of Open series boards.<\/p>\n When dealing with STM32\u2019s clock, there are a few things that need well understanding. The ARM Cortex M3 is a network of instruction\/data buses. Fore important buses of the Cortex are the Core System Clock<\/i><\/b>, Advanced High Speed Bus (AHB)<\/i><\/b>, Advanced Peripheral Bus 1 (APB1)<\/i><\/b> and Advanced Peripheral Bus 2 (APB2)<\/i><\/b>. These buses are connected as such that they are connected to the Direct Memory Access (DMA) module, SRAM, peripherals like GPIOs, ADC, timers, etc. and Cortex core. At present we need just to know about APB buses and they are of the highest importance to us. This is because we are currently dealing with the peripheral hardware of the STM32 micro and certainly not other stuffs like the DMA, Cortex core, etc. It is well known from previous posts that APB1 has a maximum operating frequency of 36MHz while APB2 can run as fast as the AHB bus \u2013 72MHz. You can now understand why GPIOs are connected to APB2 bus instead of APB1 or any other bus and how STM32 GPIOs can achieve 50MHz switching speed. APB1 bus mostly serves communication and timer modules of the STM32. APB1 frequency is not automatically scaled to have half the speed of AHB and so we need to make sure it is not overclocked by mistake. Overclocking is not a good practice and is also not recommended by any manufacturer. To avoid overclocking the APB1 bus always use at least a prescaler of 2 whenever driving the STM32 beyond 36MHz.<\/p>\n Lastly we can also get clock output from a special pin called Microcontroller Clock Output (MCO)<\/i><\/b>. The MCO pin is usually located at PA8 pin. However to use the MCO we need to set PA8 as an Alternate Function (AFIO)<\/i><\/b> output. The MCO pin can be used to clock another micro or as a time-base for another circuit or device.<\/p>\n The code example for configuring STM32\u2019s clock and its MCO pin is literally no code at all. Everything is done by the IDE\u2019s clock configuration tool. We\u2019ll just need to configure the MCO pin. In all of the codes in this post, I used MikroC\u2019s GPIO library as it easy to use and saves a lot of time.<\/p>\n Notice how the clocks are configured. I used the HSI and didn\u2019t use the HSE. I use HSI just to show its accuracy. I used PLL as such that the 8MHz HSI is first divided by 2 before entering the PLL stage. Thus the PLL gets 4MHz input and it then multiplies this value with 2 to generate 8MHz clock. Finally The MCO outputs a clock signal of half the value of the PLL output, i.e. 4MHz. The STM32 core however runs using HSI instead of the PLL. An oscilloscope hooked with the MCO pin registers that the clock out has a frequency of 3.99MHz. It is close enough for most applications. This is the simplest demo I could imagine.<\/p>\n Video link: https:\/\/www.youtube.com\/watch?v=Fgbju2Qznkw<\/a><\/p>\n Independent Watchdog<\/span><\/p>\n As the name suggests the Independent Watchdog (hereinafter referred as IWDG) is a completely independent watchdog timer. It has separate dedicated clock and it remains operational even if the main clock of a STM32 micro fails. Thus IWDG is suited especially for those applications where it is needed just to reset a STM32 MCU on failure or due to a hang up. This is just like the regular watchdog timer use in common 8 bit MCUs. There is nothing complex about it.<\/p>\n The dedicated separate clock of the IWDG hardware comes from Low Speed Internal (LSI) clock. It is not an accurate one as one might expect. This inaccuracy is due to the fact that the LSI is a RC oscillator. It has an oscillation frequency of somewhat between 30 \u2013 60 kHz. For most applications it is assumed to have a mean frequency of 45 kHz though it is supposed to be around 32 kHz. This assumption makes it simple although there will be some deviation. Shown below is the internal block diagram of IWDG hardware:<\/p>\n There are a few registers associated with IWDG and the register map for IWDG is shown below:<\/p>\n Activating the IWDG is straight. All we need to do is to load the Key Register IWDG_KR<\/i><\/b> with a predefined constant 0xCCCC<\/i>. Once loaded with this value the IWDG hardware is initiated and its counter will down count from a reset value 0xFFF or a preloaded value to 0x000. When the counter counts to 0x000 count, a reset signal is issued. This is normally what we will not be wanting and so to avoid the reset we need to rewrite IWDG_KR<\/i><\/b> with 0xAAAA<\/i>. This will reload the counter and thus reset is avoided. At this point it is pretty much clear that we will periodically need to write 0xAAAA<\/i> to the IWDG_KR<\/i><\/b> register in the software. Should the software get stuck it will not be doing so and when time or count runs out, the IWDG will restart the MCU right from the initialization stage.<\/p>\n Before we activate the IWDG it should be configured according to our timeout need. The IWDG_PR<\/i><\/b> and IWDG_RLR<\/i><\/b> registers hold prescalar or divisor factor and reload values respectively. These values decide the required timeout before reset. These registers are by default write protected and so to alter their values we need to follow a sequence or otherwise write protection will not be removed. To configure the IWDG, we need to follow according to the steps below:<\/p>\n The formula for IWDG timeout is as follows: If, for example, RLR <\/i><\/b>equals 180, PR<\/i><\/b> equals 6 and the LSI has a frequency of 45 kHz then we roughly get a timeout of about 1000ms or 1s.<\/p>\n The code example for IWDG and the setup for it is very simple. A LED connected to PC 9 remains off until a push button connected to PA9 is pressed. This indicates initialization stage. Once pressed and held, the LED starts blinking, indicating normal operation. When the button is released, the LED stays on and then goes to reset after about one second. We, then, know for sure that the STM32 went to reset by seeing that the LED is turned off as it was during start up. ![\"Clock](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/Clock-Configuration-Tool.png\")
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![\"Open103R-Standard_l\"](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/Open103R-Standard_l.jpg\")
<\/a>Code Example:<\/h6>\n
void main()<\/span><\/pre>\n{<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 GPIO_Clk_Enable(&GPIOA_BASE);\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/Enable clock for\u00a0 GPIOA<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 GPIO_Config(&GPIOA_BASE, _GPIO_PINMASK_8, (_GPIO_CFG_MODE_ALT_FUNCTION | _GPIO_CFG_SPEED_50MHZ | _GPIO_CFG_OTYPE_PP)); \u00a0\/\/Set PA8 as a high speed digital output<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 while(1)<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 {<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/\/To do stuffs here<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 };<\/span><\/pre>\n}<\/span><\/pre>\n![\"RCC](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/RCC-1.png\")
<\/a> ![\"RCC](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/RCC-2.png\")
<\/a><\/p>\n![\"DSC_0296\"](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/DSC_0296.jpg\")
<\/a> ![\"DSC_0310\"](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/DSC_0310.jpg\")
<\/a><\/p>\n![\"IWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/IWDG-Internal-.png\")
<\/a><\/p>\n![\"IWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/IWDG-Register-Map.png\")
<\/a><\/p>\n\n
![\"IWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/IWDG-Formula.png\")
<\/a><\/p>\nCode Example:<\/h6>\n
\n<\/i><\/p>\n\/* Function prototypes *\/<\/span><\/em><\/pre>\n\u00a0<\/span><\/pre>\nvoid setup();<\/span><\/pre>\nvoid setup_GPIO();<\/span><\/pre>\nvoid setup_IWDG();<\/span><\/pre>\n\u00a0<\/span><\/pre>\nvoid main()<\/span><\/pre>\n{<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 setup();<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 while(1)<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 {<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 if(GPIOA_IDRbits.IDR9 == 0)\u00a0\u00a0 \/\/If the switch is pressed<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 {<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 GPIOC_BRRbits.BR9 = 1;\u00a0\u00a0 \u00a0\/\/Turn off LED<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 delay_ms(90);\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\/\/Wait for 90ms<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 GPIOC_BSRRbits.BS9 = 1;\u00a0 \/\/Turn on LED<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 delay_ms(90);\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/\/Wait for 90ms<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 IWDG_KR = 0xAAAA;\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\/\/Reload IWDG<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 }<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 };<\/span><\/pre>\n}<\/span><\/pre>\n\u00a0<\/span><\/pre>\nvoid setup()<\/span><\/pre>\n{<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 setup_GPIO();<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 setup_IWDG();<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 while(GPIOA_IDRbits.IDR9 == 1); \/\/Wait till the switch is pressed<\/span><\/em><\/span><\/pre>\n}<\/span><\/pre>\n\u00a0<\/span><\/pre>\nvoid setup_GPIO()<\/span><\/pre>\n{<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 GPIO_Clk_Enable(&GPIOA_BASE);\u00a0\u00a0 \/\/Enable clock for GPIOA<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 GPIO_Clk_Enable(&GPIOC_BASE);\u00a0\u00a0\u00a0\/\/Enable clock for GPIOC<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 GPIO_Config(&GPIOA_BASE, _GPIO_PINMASK_9, (_GPIO_CFG_MODE_INPUT | _GPIO_CFG_PULL_UP)); \/\/Set PA9 as a digital input with pull-up<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 GPIO_Config(&GPIOC_BASE, _GPIO_PINMASK_9, (_GPIO_CFG_MODE_OUTPUT | _GPIO_CFG_OTYPE_PP | _GPIO_CFG_SPEED_2MHZ)); \/\/Set PC9 as a digital output<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 GPIOC_BSRRbits.BS9 = 0;\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/Turn off LED<\/span><\/em><\/span><\/pre>\n}<\/span><\/pre>\n\u00a0<\/span><\/pre>\nvoid setup_IWDG()<\/span><\/pre>\n{<\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 IWDG_KR = 0x5555; \/\/Disable write protection of IWDG registers<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 IWDG_PR = 0x06;\u00a0\u00a0\u00a0\u00a0 \u00a0\/\/Set PR value<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 IWDG_RLR = 0xB4;\u00a0\u00a0\u00a0 \u00a0\/\/Set RLR value<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 IWDG_KR = 0xAAAA;\u00a0\u00a0 \u00a0\/\/Reload IWDG<\/span><\/em><\/span><\/pre>\n\u00a0\u00a0\u00a0\u00a0 IWDG_KR = 0xCCCC;\u00a0\u00a0\u00a0 \/\/Start IWDG<\/span><\/em><\/span><\/pre>\n}\n<\/span><\/pre>\n![\"IWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/IWDG-2.jpg\")
<\/a> ![\"IWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/IWDG-4.jpg\")
<\/a> ![\"IWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/IWDG-3.jpg\")
<\/a><\/p>\n
![\"WWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/WWDG-Internal-.png\")
<\/a>![\"WWDG](\"http:\/\/embedded-lab.com\/blog\/wp-content\/uploads\/2014\/11\/WWDG-Register-Map.png\")
<\/a>