Embedded Lab

Watchdog Timer – WDTA

The prime task of a watchdog timer is to reset a microcontroller should there be any software irresponsiveness. MSP430F5529’s watchdog timer, WDTA can be used like a regular watchdog timer as well as an interval timer. WDTA is similar to the previously seen WDT+ but it is a bit advanced in some areas like 32-bit counter instead of 16-bit counter. Shown below is the block diagram of WDTA:

Unlike the watchdogs of many other microcontrollers, WDTA is password protected and it means that to read/write it, a special code (0x05A) needs to be set first.

Code Example

#include "driverlib.h"
#include "delay.h"

void clock_init(void);
void GPIO_init(void);
void WDTA_init(void);

void main(void)
{
    WDT_A_hold(WDT_A_BASE);

    clock_init();
    GPIO_init();
    WDTA_init();

    while(1)
    {
        GPIO_toggleOutputOnPin(GPIO_PORT_P1,
                               GPIO_PIN0);

        delay_ms(600);

        WDT_A_resetTimer(WDT_A_BASE);

        if(GPIO_getInputPinValue(GPIO_PORT_P1,
                                 GPIO_PIN1) == false)
        {
            GPIO_setOutputHighOnPin(GPIO_PORT_P4,
                                    GPIO_PIN7);

            while(1);
        }
    };
}

void clock_init(void)
{
    PMM_setVCore(PMM_CORE_LEVEL_3);

    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P5,
                                               (GPIO_PIN4 | GPIO_PIN2));

    GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P5,
                                                (GPIO_PIN5 | GPIO_PIN3));

    UCS_setExternalClockSource(XT1_FREQ,
                               XT2_FREQ);

    UCS_turnOnXT2(UCS_XT2_DRIVE_4MHZ_8MHZ);

    UCS_turnOnLFXT1(UCS_XT1_DRIVE_3,
                    UCS_XCAP_3);

    UCS_initClockSignal(UCS_FLLREF,
                        UCS_XT2CLK_SELECT,
                        UCS_CLOCK_DIVIDER_4);

    UCS_initFLLSettle(MCLK_KHZ,
                      MCLK_FLLREF_RATIO);

    UCS_initClockSignal(UCS_SMCLK,
                        UCS_XT2CLK_SELECT,
                        UCS_CLOCK_DIVIDER_2);

    UCS_initClockSignal(UCS_ACLK,
                        UCS_XT1CLK_SELECT,
                        UCS_CLOCK_DIVIDER_1);
}

void GPIO_init(void)
{
    GPIO_setAsInputPinWithPullUpResistor(GPIO_PORT_P1,
                                         GPIO_PIN1);

    GPIO_setAsOutputPin(GPIO_PORT_P1,
                        GPIO_PIN0);

    GPIO_setDriveStrength(GPIO_PORT_P1,
                          GPIO_PIN0,
                          GPIO_FULL_OUTPUT_DRIVE_STRENGTH);

    GPIO_setAsOutputPin(GPIO_PORT_P4,
                        GPIO_PIN7);
    GPIO_setDriveStrength(GPIO_PORT_P4,
                          GPIO_PIN7,
                          GPIO_FULL_OUTPUT_DRIVE_STRENGTH);

    GPIO_setOutputLowOnPin(GPIO_PORT_P1,
                           GPIO_PIN0);

    GPIO_setOutputLowOnPin(GPIO_PORT_P4,
                           GPIO_PIN7);
}

void WDTA_init(void)
{
    WDT_A_initWatchdogTimer(WDT_A_BASE,
                            WDT_A_CLOCKSOURCE_VLOCLK,
                            WDT_A_CLOCKDIVIDER_32K);

    WDT_A_start(WDT_A_BASE);

    WDT_A_resetTimer(WDT_A_BASE);
}

Hardware Setup

Explanation

After power-on reset, WDTA is configured in watchdog mode with an approximate initial 32 ms reset interval. Unless commanded to stop immediately, it will keep resetting MCU. This is why at the start of every program the following code is placed:

WDT_A_hold(WDT_A_BASE);

This piece of code disables WDTA until reconfigured and reused.

To setup WDTA in watchdog mode, we need to specify its source of clock signal. In this example, it is VLOCLK. We also need to decide the WDTA clock divider in order to achieve the required amount of period.  

void WDTA_init(void)
{
    WDT_A_initWatchdogTimer(WDT_A_BASE, WDT_A_CLOCKSOURCE_VLOCLK, WDT_A_CLOCKDIVIDER_32K);

    WDT_A_start(WDT_A_BASE);

    WDT_A_resetTimer(WDT_A_BASE);
}

Here the time period according to the settings is about 3 seconds (32000 / 10 kHz). If WDTA is not reset within this time window, a reset will be triggered.

In the main, P1.0 LED is toggled every 600ms and WDTA is reset. Thus, WDTA counter is reset 5 times earlier than reset interval. This goes on until P1.1 push button is pressed. When the button is pressed, P4.7 LED is lit and a predefined intentional software loop is entered. Since WDTA counter is no longer reset in the loop, WDTA counter keeps ticking and a reset occurs after 3 seconds, starting everything from the beginning.

GPIO_toggleOutputOnPin(GPIO_PORT_P1, GPIO_PIN0);

delay_ms(600);

WDT_A_resetTimer(WDT_A_BASE);

if(GPIO_getInputPinValue(GPIO_PORT_P1, GPIO_PIN1) == false)
{
   GPIO_setOutputHighOnPin(GPIO_PORT_P4, GPIO_PIN7);

   while(1);
}

Note that after reset, RAM data are usually not erased unless modified or reinitialized. However, in real life applications, RAM data may be corrupted because something unusual caused the reset to occur. Therefore, we can use CRC or other means to check RAM data integrity if past data are needed.

Demo

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